1. Field of the Invention
This invention relates to semiconductor memories where the address decoder is placed in the center of the data field, and particularly relates to read only memories (ROM's) utilizing Integrated Schottky logic (ISL) or metal-semiconductor field effect transistors (MESFET) gates as word line drivers in conjunction with Schottky diode memory arrays.
2. Prior Art
Semiconductor memories seek to maximize packing density, minimize power dissipated, afford maximum speed of read and write operations and seek to provide memory chips which are easily processed to be fully functional. Diode data fields are advantageous because they usually exhibit high yield and afford relatively high packing density. This is particularly true of Schottky diode arrays because of the high yield in processing Schottky diodes. Examples of a read or reproduced only storage (ROS) matrix and a transistor switching circuit where Schottky diodes form memory arrays are U.S. Pat. Nos. 4,347,585 issued to Eardley and 4,276,617 issued to Le, respectively.
In the Eardley patent complex TTL word line gates (such as gate 19A) and complicated sense amplifiers (such as amplifier 86A) each involving several transistors, are employed. This necessitates the use of relatively large chip areas for the gates. In Le, two types of Schottky diode barriers (i.e., high barrier diodes such as diodes 31-nn and 70-7n and low barrier diodes such as 90-9n) are included in the circuit. The use of two types of Schottky diodes entails more complicated processing than if only one Schottky diode type were employed. Additionally, both Le and Eardley place their circuits' address decoders (in Le see circuits 110 and 120 and in Eardly see circuits 19A and 40A) on the periphery of the data field memory arrays. For a data bit located at the extreme of the field from either the column or row driver, or both, this necessitates the maximum voltage drop along the corresponding bit and/or word line in order to affect data at the remote location. It would be preferable to reduce the voltage drop needed to affect data at remote locations for a given memory size relative to the configurations of Eardly or Le. Reductions in the voltage drop would reduce the noise margin and thus soften the design margin or allow more data bits to be designed within a circuit for a given noise margin than configurations such as Eardley or Le.